Resistive memory is a new class of non-volatile memory, which can retain the stored information when powered off. A resistive memory device normally comprises an array of memory cells, each of which includes at least a resistive memory element and a selection element coupled in series between appropriate electrodes. Upon application of an appropriate voltage or current to the resistive memory element, the electrical resistance of the resistive memory element would change accordingly, thereby switching the stored logic in the respective memory cell.
A resistive memory element can be classified into at least one of several known groups based on its resistively switching mechanism. The resistive memory element of Phase Change Random Access Memory (PCRAM) may comprise a phase change chalcogenide compound, which can switch between a resistive amorphous phase and a conductive crystalline phase. The resistive memory element of Conductive Bridging Random Access Memory (CBRAM) relies on the statistical bridging of metal rich precipitates therein for its switching mechanism. The resistive memory element of CBRAM normally comprises a nominally insulating metal oxide material, which can switch to a lower electrical resistance state as the metal rich precipitates grow and link to form conductive paths upon application of an appropriate voltage. The resistive memory element of Magnetoresistive Random Access Memory (MRAM) typically comprises at least two layers of different ferromagnetic materials with a non-magnetic spacer layer interposed therebetween. When a switching pulse is applied to the memory element of a MRAM device, one of the ferromagnetic layers will switch its magnetic field polarity, thereby changing the element's electrical resistance.
A selection element in a memory cell functions like a switch to direct current through the selected memory element coupled thereto. One common selection element is diode, which can reverse bias a non-selected memory cell. While a selection diode has a simple structure that can minimize the cell size of the resistive memory cell, a memory architecture employing the selection diode normally has a slower random access time. Another commonly used selection element is transistor, which allows for faster selection of memory cells and therefore faster random access time. While a memory device employing the selection transistor is more suitable for the random access type of memories, the more complicated structure of the selection transistor means the size of the memory cell will be larger, which translates to a lower cell density. Moreover, the memory device utilizing the selection transistor needs additional wiring for controlling the gate electrode, further complicating the scaling of the device.
To be cost competitive, a small memory cell size is desired in order to increase device density. One way to achieve this is to simply shrink the feature size, F, normally associated with a particular lithography process. However, several difficulties can arise when scaling down a conventional transistor, particularly its channel length, to sizes of a few tens of nanometers. As the channel length is reduced, there is a propensity for the formation of parasitic conduction paths between source and drain, thereby causing punch through current leakages. Another obstacle encountered in shrinking the conventional transistor is reduced current drivability caused by the reduced width of the current carrying channel. This is a significant issue for resistive memory devices, which require higher current to switch their memory state.
Another approach to reduce the memory cell size is to use a different architecture that would permit the memory cell size to scale down while increasing the channel width and length to mitigate the above mentioned problems associated with shrinking feature size. With the source, drain, and channel of the conventional selection transistor lie on a same plane, the conventional resistive memory cell size is limited to 8 F2. As would be understood by one of ordinary skill in the art, the minimum pitch between two repetitive features on a same mask layer is 2 F. Accordingly, the minimum size of a memory cell would be 4 F2 when arranged in a square array using conventional lithography.
To attain a cell size of 4 F2 would require the channel of the selection transistor to be placed in such a way that allows the current to flow in a vertical direction perpendicular to the substrate plane. FIG. 1 illustrates a memory device having an array of 4 F2 memory cells 80, each of which comprising a memory element 82 connected to a vertical selection transistor 84 by way of a contact stud 86. The vertical selection transistor 84 includes a drain region 88 disposed on top of a trench sidewall, a shared source region 90 disposed on the trench bottom, and a gate 92 formed on the trench sidewall, enabling current to flow vertically between the shared source 90 and drain region 88 by way of a vertical channel formed on the sidewall. It should be noted that while the memory cells 80 in FIG. 1 can be arranged to have a size of 4 F2, the design and placement of gate, source, and bit electrodes connected to the cells is critical in preserving this minimum memory cell size for memory devices wherein multiple electrodes pass through each memory cell. Moreover, local gate, source, and bit electrodes coupled to an array of memory cells need to be connected to main wiring lines, such as word lines, bit lines, and source lines. For the 4 F2 memory array illustrated in FIG. 1 wherein each cell has a cross section dimension of 2 F to accommodate a gate electrode and a source electrode in a same direction, it remains a challenge to construct the connections between the local electrodes and the main wiring lines such that both layout complexity and space usage are minimized.